1. Field of the Invention
The present invention relates to a memory device.
2. Description of the Related Art
Semiconductor memory has become increasingly popular for use in various electronic devices. For example, non-volatile semiconductor memory is used in cellular telephones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices and other devices. Electrically Erasable Programmable Read Only Memory (EEPROM) and flash memory are among the most popular non-volatile semiconductor memories. With flash memory, also a type of EEPROM, the contents of the whole memory array, or of a portion of the memory, can be erased in one step, in contrast to the traditional, full-featured EEPROM.
Both the traditional EEPROM and the flash memory utilize a floating gate that is positioned above and insulated from a channel region in a semiconductor substrate. The floating gate is positioned between the source and drain regions. A control gate is provided over and insulated from the floating gate. The threshold voltage (VTH) of the transistor thus formed is controlled by the amount of charge that is retained on the floating gate. That is, the minimum amount of voltage that must be applied to the control gate before the transistor is turned on to permit conduction between its source and drain is controlled by the level of charge on the floating gate.
Some EEPROM and flash memory devices have a floating gate that is used to store two ranges of charges and, therefore, the memory element can be programmed/erased between two states, e.g., an erased state and a programmed state. Such a flash memory device is sometimes referred to as a binary flash memory device because each memory element can store one bit of data.
A multi-state (also called multi-level) flash memory device is implemented by identifying multiple distinct allowed/valid programmed threshold voltage ranges. Each distinct threshold voltage range corresponds to a predetermined value for the set of data bits encoded in the memory device. For example, each memory element can store two bits of data when the element can be placed in one of four discrete charge bands corresponding to four distinct threshold voltage ranges.
Typically, a program voltage VPGM applied to the control gate during a program operation is applied as a series of pulses that increase in magnitude over time. In practice, the program voltage is applied to a word line which is in communication with the control gates of a number of storage elements. In fact, the control gates may be formed from portions of the word lines. In one possible approach, the magnitude of the pulses is increased with each successive pulse by a predetermined step size, e.g., 0.2-0.4 V. VPGM can be applied to the control gates of flash memory elements. In the periods between the program pulses, verify operations are carried out. That is, the programming level of each element of a group of elements being programmed in parallel is read between successive programming pulses to determine whether it is equal to or greater than a verify level to which the element is being programmed. For arrays of multi-state flash memory elements, a verification step may be performed for each state of an element to determine whether the element has reached its data-associated verify level. For example, a multi-state memory element capable of storing data in four states may need to perform verify operations for three compare points. The verification involves applying a series of verify voltages to the word line which is in communication with the storage elements which are being read, and sensing, for each verify voltage, whether the storage elements are conductive, via associated bit lines and sense amplifiers.
Moreover, when programming an EEPROM or flash memory device, such as a NAND flash memory device in a NAND string, typically VPGM is applied to the control gate and the bit line is grounded, causing electrons from the channel of a cell or memory element, e.g., storage element, to be injected into the floating gate. When electrons accumulate in the floating gate, the floating gate becomes negatively charged and the threshold voltage of the memory element is raised so that the memory element is considered to be in a programmed state. More information about such programming can be found in U.S. Pat. Nos. 6,859,397 and 6,917,542, both of which are incorporated herein by reference in their entirety.
Further, during a read operation which occurs after programming, a series of read reference voltages are applied to a set of storage elements to be read, and a determination is made as to which read reference voltage causes a storage element to become conductive. The read reference voltages are set to allow different data states of the storage elements to be distinguished. For example, if there are n possible data states used, it is typically necessary to apply n−1 read voltage levels sequentially to a storage element to ascertain the state of the storage element. The verification, which occurs as part of the programming process, and the reading, which occurs after programming, can both be considered to be read operations.
However, such read operations typically require a delay which is set based on the propagation time of the verify or read voltage along the entire word line. As a result, throughput is not always optimized.